Current Time:


-= HOME =-

-= BLOG =-

-== BIO ==-


-=MY LAB=-



-= LINKS =-

-= VHDL =-



Gerry's Messy Electronics/Robotics

Click the button below to go Back to the "CHIPPERY " section of my Lab

-= BACK =-



DATA I/O Universal Programmer





So a couple of years ago I acquired a DATA I/O "Labsite" Universal programmer with the 84 pin
socket adapter that accepts the Altera MAX 7000 84 pin chips. I had to search the net for like three months to find the software for this badboy and found a user in an Arcade restoring forum that had it on an old 386 harddrive, what luck!!

This version of the Labsite software that I got (Version 6.2) which was the last
available version from Data I/O, supports the 84 pin PLCC socket adapter. The 84-Pin adapter was actually the main reason I bought the unit in the first place. I wanted to erase a load of Altera MAX EPM7128SLC-84 CPLDs I had bought years before, and was not able to use them since I got them.

So here's the deal with some of Atera's vintage MAX series chips. EPLD's like the Altera 7128SLC84 have JTAG programming communication inputs also referred to as ISP communication, but these are actually two seperate types of programming. (SEE MY PAGE ON JTAG & ISP) So now, the CPLD Logic designer or programmer has the option to have these "JTAG" interface Pins be converted to input/output lines for interfacing purposes, once the programming of the chip is completed. So if you are using the JTAG interface to Program the CPLD, this will therefore disconnect the JTAG port permanently after the programming process has completed. You can therefore no longer re-program the CPLD with a JTAG interface after this has occured. Unfortunately most $150 dollar range Altera college and university development boards are only equipped with a JTAG interface for programming. So you are out of luck to try and reprogram a Chip that has had the JTAG interface disabled, or switched over to be used as standard I/O pins. The whole communication problem is simply because the JTAG is just disabled, the chip is not actually damaged or faulty at all, which many users are lead to believe.

This is a common problem many student/hobbyists encounter when they buy second hand Chips off the net like Ebay, which is exactly what happened to me. The chips are useless as far as JTAG programming goes. The only way to have the JTAG
communication lines restored is to use a NON-JTAG programmer Like the Altera Master Programming unit or a third party programmer like the DATA I/O Labsite or Unisite. Using these programmers to erase the chips, reconnects or enables the JTAG communication lines, back to their factory default setting just like when you first purchased the chips new.

This particular mode for the Altera chips is referred to as "JTAG LOCKOUT". Altera doesn't really talk about this in their datasheets and it is just a real pain in the ass. However, the issue is now solved finally after over a year of researching this problem and a big thanks goes out to a buddy of mine named Will.

Thanks a mint Will!

So If any of you need to have your Altera MAX chips erased for JTAG programming let me know. I have a running setup to do just that. I erased 35 chips the first night I got the LabSite up and running, it was awesome. I also have the Altera Master Programming Unit, so I can use either system to re-enable the JTAG programming interface.

At the beginnig of my search for the Labsite software, I opened up a Yahoo Group Strictly devoted to DATA I/O Universal Programmers hoping people would join. Well, there are over 250 members to date and growing. There are even some former DATA I/O Employees that have joined. Many knowledgable people are availalbe to help you get your DATA I/O programmers up and running. The group link is shown below:


If you're into the older Altera CPLD's you can Join my Altera Yahoo Group: